Method and apparatus for coupling integrated circuit packages to bonding pads having vias

ABSTRACT

The electrical contacts of an integrated circuit package are coupled to printed circuit board bonding pads that include vias having via channels. In one embodiment, a method for fabricating an electronic assembly utilizes a mask having at least one aperture that overlies the bonding pad without substantially overlying the bonding pad&#39;s via channel. The aperture can be of any shape, including a circle, ellipse, polygon, or a free-form shape. Solder paste is screened through the mask onto the printed circuit board pads but not the via channels. The electrical contacts of a surface mount technology component such as a ball grid array component can then be affixed to the bonding pads using a reflow soldering technique according to one embodiment.

[0001] This application is a divisional of application U.S. Ser. No.09/525,399, filed on Mar. 15, 2000.

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates generally to electronics packaging.More particularly, the present invention relates to a method andapparatus for coupling the electrical contacts of an integrated circuitpackage to bonding pads having vias.

BACKGROUND OF THE INVENTION

[0003] Integrated circuits (ICs) are typically assembled into packagesthat are physically and electrically coupled to a substrate such as aprinted circuit board (PCB) to form an “electronic assembly”. The“electronic assembly” can be part of an “electronic system”. An“electronic system” is broadly defined herein as any product comprisingan “electronic assembly”. Examples of electronic systems includecomputers (e.g., desktop, laptop, hand-held, server, etc.), wirelesscommunications devices (e.g., cellular phones, cordless phones, pagers,etc.), computer-related peripherals (e.g., printers, scanners, monitors,etc.), entertainment devices (e.g., televisions, radios, stereos, tapeand compact disc players, video cassette recorders, etc.), and the like.

[0004] In the field of electronic systems there is an incessantcompetitive pressure among manufacturers to drive the performance oftheir equipment up while driving down production costs. This isparticularly true regarding the packaging of ICs on substrates, whereeach new generation of board-level packaging must provide increasedperformance while generally being smaller or more compact in size.

[0005] A substrate typically includes a number of insulation and metallayers selectively patterned to provide metal interconnect lines(referred to herein as “traces”), and a plurality of electroniccomponents mounted on one or more surfaces of the substrate andfunctionally interconnected through the traces. The routing tracestypically carry signals that are transmitted between the electroniccomponents, such as ICs, of the system. Some ICs have a relatively largenumber of input/output (I/O) pads. The large number of I/O pads requiresa relatively large number of routing traces. Some PCBs require multiplelayers of routing traces to accommodate all of the systeminterconnections.

[0006] Routing traces located within different layers are typicallyconnected electrically by vias formed in the board. A via can be made bymaking a hole through some or all layers of a PCB and then coating orplating the interior hole surface with an electrically conductivematerial, such as copper or tungsten.

[0007] One of the conventional ways of mounting components on asubstrate is called surface mount technology (SMT). SMT components haveterminations or leads (generally referred to as “electrical contacts”)that are soldered directly to the surface of the substrate. SMTcomponents are widely used because of their compact size and simplicityof mounting. One conventional type of SMT component utilizes a ball gridarray (BGA) to connect to the substrate. A BGA component has a pluralityof solder balls on one surface, each of which represents an electricalcontact. Each solder ball connects to a conductor within the component.

[0008] The electrical contacts of an SMT component, such as a BGAcomponent, are coupled to corresponding metallized mounting or bondingpads (also referred to herein as “lands”) on the surface of thesubstrate, in order to establish a secure physical connection to thesubstrate as well as to establish an electrical connection between theSMT component and at least one trace connected to the lands. Ordinarilyone land is dedicated to one SMT electrical contact.

[0009] Prior to mounting the SMT component on a substrate, the substrateis selectively coated with solder paste, using a mask (also referred toin the art as a stencil or a solder mask stencil) that permits solderpaste to coat just the lands. To mount an SMT component to a substrate,the component is carefully positioned or “registered” over the substrateso that its electrical contacts are aligned with the correspondinglands. Finally, the entire package is heated to a temperature that meltsthe solder balls and the solder paste, so that they physically merge andform proper electrical and physical connections

[0010] For the reasons stated above, and for other reasons stated belowwhich will become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a significant need inthe art for a method and apparatus for coupling an integrated circuitpackage to a substrate that offers relatively high density whileproviding a relatively high quality interconnection.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 is a perspective view of a prior art PCB and mask;

[0012]FIG. 2 is a perspective view of apparatus for forming at least oneconductive bonding area on a land of a PCB in accordance with oneembodiment of the invention;

[0013]FIG. 3 is a perspective view of a PCB in accordance with oneembodiment of the invention;

[0014]FIG. 4 is a perspective view of an integrated circuit positionedfor mounting on a PCB in accordance with one embodiment of theinvention;

[0015]FIG. 5 is a perspective view of a PCB having areas of conductivematerial in accordance with an alternate embodiment of the invention;

[0016]FIG. 6 is a perspective view of a PCB having areas of conductivematerial in accordance with another alternate embodiment of theinvention;

[0017]FIG. 7 is a perspective view of a PCB having areas of conductivematerial in accordance with yet another alternate embodiment of theinvention;

[0018]FIG. 8 is a perspective view of a PCB having areas of conductivematerial in accordance with a further alternate embodiment of theinvention; and

[0019]FIG. 9 is a flow diagram of a method of fabricating an electronicassembly that includes coupling an integrated circuit to a PCB with apad having a via, in accordance with one embodiment of the invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0020] In the following detailed description of embodiments of theinvention, reference is made to the accompanying drawings which form apart hereof, and in which is shown by way of illustration specificpreferred embodiments in which the inventions may be practiced. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention, and it is to be understood thatother embodiments may be utilized and that logical, mechanical andelectrical changes may be made without departing from the spirit andscope of the present inventions. The following detailed description is,therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined only by the appended claims.

[0021]FIG. 1 is a perspective view of a prior art PCB 1 and mask 2. PCB1 has at least one land or bonding pad 3. Land 3 is made of anelectrically conductive material such as copper. Mask 2 has an aperture4 of approximately the same shape and size as land 3. There are commonlya plurality of lands 3 on PCB 1 and a corresponding plurality ofapertures 4 in mask 2, but for simplicity of illustration just one ofeach has been shown in FIG. 1. Aperture 4 of mask 2 is positioned or“registered” directly over land 3, and solder paste is directed througheach aperture 4 onto each land 3 but not onto any other part of PCB 1.For the prior art arrangement illustrated in FIG. 1, solder paste isdirected onto the entire area of land 3.

[0022]FIG. 2 is a perspective view of apparatus for forming at least oneconductive bonding area 16, 18 on a land 12 of a PCB 10 in accordancewith one embodiment of the invention. PCB 10 has at least one land 12.Land 12 is the upper surface of the channel wall of a through-hole orvia 14. Although in the IC packaging technology vias can be either solidor hollow, as used herein the term “via” means a hollow via. Via 14 hasa hole or channel 15 through it.

[0023] Via 14 comprises electrically conductive material, such ascopper, that electrically connects circuit traces on different layers(not shown) of PCB 10. Via 14 and its channel 15 can be of any type orcross-section but are typically circular. In the embodiment illustratedin FIG. 2, via 14 is essentially a copper cylinder having a wall offinite thickness that extends partially into PCB 10 (as indicated by thedashed lines) or entirely through PCB 10, depending upon how many layersof the PCB it is required to connect to.

[0024] By using the exposed upper surface of via 14 as a land 12,valuable “real estate” is conserved on PCB 10 that would otherwise beseparately occupied by via 14 and land 12. When this savings ismultiplied by potentially hundreds of via-in-lands on a PCB, the overallsavings is considerable, allowing relatively more components to bemounted on a PCB of equivalent size or allowing a PCB with the samenumber of components to be reduced in size. The resulting electronicsystem can be manufactured at a lower cost and in a more compact size,and is therefore more commercially attractive.

[0025] To avoid deleterious problems that could result if the channel 15of via 14 is filled with solder, mask 20 comprises at least one aperture16, 18 that overlies the land 12 but not any substantial portion ofchannel 15 when mask 20 is properly registered with respect to PCB 10.The aperture 16, 18 has any suitable geometry, such as a circle,ellipse, polygon, multi-sided shape, or free-form shape. In oneembodiment, two apertures 16 and 18 are provided in mask 20 for eachland 12, one aperture 16 being located on the exposed surface of thewall of via 14 on one side of channel 15, and the other aperture 18located on the exposed surface of the wall of via 14 on another side(not necessarily opposite) of channel 15. In other embodiments, fewer ormore than two apertures 16, 18 can be employed. In one embodiment, theapertures have the same shape, but in other embodiments the aperturescan have different shapes for the same PCB or even the same land.

[0026] When mask 20 has been properly registered with respect to PCB 10,a fabricating machine comprising a solder paste screener 30 dispenses anelectrically conductive material, such as a mixture of solder and solderflux, to mask 20. The electrically conductive material, representedschematically by dashed arrows 31, goes through apertures 16,18 onto PCB10.

[0027]FIG. 3 is a perspective view of a PCB 10 in accordance with oneembodiment of the invention. As a result of the electrically conductivematerial being dispensed onto PCB 10 through mask 20 (FIG. 2), land 12has affixed thereto at least one area 26, 28 that comprises a layer ofelectrically conductive material, and that does not substantiallyoverlie channel 15. That is, the layer of electrically conductivematerial avoids overlying any substantial portion of channel 15. In oneembodiment, two areas 26 and 28 are provided for each land 12, one area26 being located on one side of channel 15, and the other area 28located on another side (not necessarily opposite) of channel 15. Inother embodiments, fewer or more than two areas 26, 28 can be employed.

[0028]FIG. 4 is a perspective view of an integrated circuit (IC) 40positioned for mounting on a PCB 10 in accordance with one embodiment ofthe invention. PCB 10 and IC 40 form an electronic assembly that can bepart of an electronic system. IC 40 can be a surface mount technologycomponent, such as a ball grid array device having at least one ball 45of electrically conductive material such as solder. When IC 40 isproperly registered over PCB 10, ball 45 is positioned over land 12,including solder paste deposits 26 and 28. Ball 45 is then positioned onland 12 and affixed to land 12. In one embodiment, ball 45 is affixed toland 12 by heating the electrically conductive material substantially toits melting point, so that ball 45 and areas 26, 28 flow together andbecome physically and electrically coupled upon cooling.

[0029] In one embodiment, the electrically conductive material comprisessolder and solder flux. As the solder is being heated to its meltingpoint, the solder flux first substantially reaches its vapor point. Ifsolder and solder flux were allowed to be deposited into channel 15, asthe temperature is raised to reflow temperature, the solder flux wouldfirst vaporize and expand. The solder flux in the solder paste on theland would melt before the solder flux in the via's channel 15, thussealing the liquid solder flux in the via. In order for the liquid fluxin the via to escape, it would need to overcome the weight of theelectrical component as well as the flux seal between the ball and theland. When the ball begins to reflow and bond to the land, the forcesrequired for the flux in the via to escape are exponentially increased.The vaporized flux inside the via tries to escape and can go into thesolder ball, causing a ballooning effect that can be very deleterious,because adjacent solder balls can touch and cause an electrical short.The present invention solves this problem by keeping solder paste out ofthe channel 15 of via 14.

[0030]FIG. 5 is a perspective view of a PCB 10 having areas 51, 52 ofconductive material in accordance with an alternate embodiment of theinvention. Areas 51 and 52 are shaped like squares or diamonds.

[0031]FIG. 6 is a perspective view of a PCB 10 having areas 61, 62 ofconductive material in accordance with another alternate embodiment ofthe invention. Areas 61 and 62 are triangular in shape.

[0032]FIG. 7 is a perspective view of a PCB 10 having areas 71, 72 ofconductive material in accordance with yet another alternate embodimentof the invention. Areas 71 and 72 are rectangular in shape.

[0033]FIG. 8 is a perspective view of a PCB 10 having areas 81, 82 ofconductive material in accordance with a further alternate embodiment ofthe invention. Areas 81 and 82 are free-form in shape and can be of anyappropriate shape that achieves a reliable connection between theelectrical contacts of the component and the corresponding lands.

[0034] In FIGS. 5-8, areas 51, 52, 61, 62, 71, 72, 81, and 82 can bepositioned in any suitable orientation, and they do not necessarily haveto be positioned as shown in the illustrations.

[0035]FIG. 9 is a flow diagram of a method of fabricating an electronicassembly that includes coupling an integrated circuit to a PCB with apad having a via, in accordance with one embodiment of the invention.The method begins in 101.

[0036] In 103, a land is formed on a surface of a substrate, such as aPCB. The land has a via having an exposed channel wall and an opening.The via is formed in the PCB through conventional techniques. Theexposed surface of the via can function as the land.

[0037] In 105, a mask is positioned over the surface of the substrate.The mask comprises at least one aperture that overlies a portion of thevia's exposed channel wall without substantially overlying the via'schannel or opening.

[0038] In 107, an electrically conductive material, such as solderpaste, is applied to the via's exposed channel wall through the at leastone aperture of the mask while it is positioned over the surface of thesubstrate.

[0039] In 109, an electrical contact of an IC ball grid array ispositioned on the land.

[0040] In 111, the electrical contact is affixed to the land. This canbe accomplished, for example, by reflow soldering. The method ends in120.

[0041] PCB 10 can be any type of electrical substrate on whichelectrical components can be mounted, such as a material formed ofpolyimide, a suitable organic material, silicon, glass, quartz, ceramic,and the like.

[0042] The electrical component that is mounted to PCB 10 can be of anytype, such as an IC or other semiconductor device; a passive elementsuch as an inductor, capacitor, or resistor; or any other kind ofelectrical or electronic device. IC 40 can be of any type, such as amicroprocessor or microcontroller, memory circuit, application specificintegrated circuit (ASIC), digital signal processor (DSP), a radiofrequency circuit, an amplifier, a power converter, a filter, a clockingcircuit, and the like.

CONCLUSION

[0043] The present invention conserves valuable PCB “real estate” byutilizing lands comprising vias, while at the same time providingsatisfactory reliability of the solder connections between theelectrical contacts of electronic component packages, such as surfacemount technology components, e.g. ball grid array devices, andcorresponding lands on the PCB. If solder were permitted to be screenedinto the via channels, a significant problem can occur in the form ofsolder flux vaporizing and expanding into solder balls to the extentthat adjoining solder balls can come into contact with each other. Amongother advantages, the present invention solves this problem bypreventing solder and solder flux from entering into the via channels inthe lands.

[0044] As shown herein, the present invention can be implemented in anumber of different embodiments, including a method for fabricating anelectronic assembly, an IC package, a mask for use in fabricating an ICpackage, a machine for fabricating an electronic assembly, an improvedsubstrate or PCB, and an electronic system.

[0045] Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. Therefore, it is manifestly intended that this invention belimited only by the claims and the equivalents thereof.

What is claimed is:
 1. A method for fabricating an electronic assemblycomprising: forming a land on a surface of a printed circuit boardsubstrate, the land having a via with an exposed channel wall and anopening; positioning a mask over the surface of the substrate, the maskcomprising at least one aperture that overlies a portion of the exposedchannel wall without substantially overlying the opening; and applyingan electrically conductive material to the portion of the exposedchannel wall through the at least one aperture of the mask while it ispositioned over the surface of the substrate.
 2. The method recited inclaim 1 wherein, in the positioning operation, the aperture has ageometry from the group consisting of a circle, an ellipse, a polygon,and a free-form shape.
 3. The method recited in claim 1 wherein, in theforming operation, the via extends into the substrate.
 4. The methodrecited in claim 1 wherein the electronic assembly is to receive anintegrated circuit package.
 5. The method recited in claim 1 wherein theelectronic assembly is to receive an integrated circuit packagecomprising a ball grid array of electrical contacts, the method furthercomprising: positioning one of the electrical contacts on the land; andaffixing the one of the electrical contacts to the land.
 6. The methodrecited in claim 5 wherein affixing comprises heating the electricallyconductive material substantially to its melting point.
 7. The methodrecited in claim 6 wherein, in the applying operation the electricallyconductive material is mixed with flux, and wherein affixing comprisesheating the flux substantially to its vapor point.
 8. A mask for use infabricating an electronic assembly, wherein the electronic assemblycomprises a printed circuit board substrate having at least one landwith a via having a channel, the mask comprising at least one aperturethat overlies the land but not any substantial portion of the via'schannel when the mask is registered with respect to the substrate. 9.The mask recited in claim 8, wherein the aperture has a geometry fromthe group consisting of a circle, an ellipse, a polygon, and a free-formshape.
 10. The mask recited in claim 8 and comprising two apertures perland.
 11. The mask recited in claim 8 wherein an electrically conductivematerial can be applied to the substrate through the at least oneaperture.
 12. The mask recited in claim 11 wherein the electricallyconductive material comprises solder.
 13. The mask recited in claim 12wherein the electrically conductive material is mixed with a flux. 14.An integrated circuit package comprising: a substrate; at least one landon the substrate, the land having a via with an exposed channel wall andan opening, and the land having affixed thereto at least one area thatcomprises a layer of electrically conductive material that overlies aportion of the exposed channel wall without substantially overlying theopening.
 15. The integrated circuit recited in claim 14, wherein thearea has a geometry from the group consisting of a circle, an ellipse, apolygon, and a free-form shape.
 16. The integrated circuit recited inclaim 14 and comprising two areas per land.
 17. The integrated circuitrecited in claim 14 wherein the via extends into the substrate.
 18. Theintegrated circuit recited in claim 14 and further comprising: a surfacemount technology component affixed to the land with the electricallyconductive material.
 19. The integrated circuit recited in claim 14wherein the electrically conductive material comprises solder.
 20. Theintegrated circuit recited in claim 14 wherein the electricallyconductive material is mixed with a flux.
 21. A machine for fabricatingan electronic assembly, the electronic assembly comprising a land on asurface of a substrate, the land having a via channel therein, themachine comprising: a mask comprising at least one aperture to overliethe land but not any substantial portion of the via channel when themask is registered with respect to the substrate; and a solder pastescreener to dispense solder paste through the at least one aperture. 22.The machine recited in claim 21, wherein the aperture has a geometryfrom the group consisting of a circle, an ellipse, a polygon, and afree-form shape.
 23. A substrate comprising at least one land, the landhaving a via channel therein, and the land having affixed thereto atleast one area that comprises a layer of electrically conductivematerial and that substantially avoids overlying the via channel. 24.The substrate recited in claim 23, wherein the area has a geometry fromthe group consisting of a circle, an ellipse, a polygon, and a free-formshape.
 25. The substrate recited in claim 23 and comprising two areasper land.
 26. The substrate recited in claim 23 wherein the via goesextends through the substrate.
 27. The substrate recited in claim 23 andfurther comprising a surface mount technology component affixed to theland with the electrically conductive material.
 28. The substraterecited in claim 23 wherein the electrically conductive materialcomprises solder.
 29. An electronic system comprising an integratedcircuit package having a substrate, at least one land on the substrate,the land having a via channel therein, and the land having affixedthereto at least one area that comprises a layer of electricallyconductive material and that substantially avoids overlying the viachannel.
 30. The electronic system recited in claim 29 wherein the areahas a geometry from the group consisting of a circle, an ellipse, apolygon, and a free-form shape, the electronic system further comprisinga surface mount technology component affixed to the land with theelectrically conductive material.